74AUP1G79GX,125 Overview

4-XFDFN Exposed Padis the way it is packaged. You can find it in the Tape & Reel (TR)package. This output is configured with Non-Inverted. JK flip flop uses Positive Edgeas the trigger. The electronic part is mounted in the way of Surface Mount. With a supply voltage of 0.8V~3.6V volts, it operates. The operating temperature is -40°C~125°C TA. Logic flip flops of this type are classified as D-Type. JK flip flop is a part of the 74AUPseries of FPGAs. Its output frequency should not exceed 309MHz Hz. In total, there are 1 elements. Currently, there are 5 terminations. D latch belongs to the 74AUP1G79 family. Power is supplied from a voltage of 1.1V volts. A JK flip flop with a 0.8pFfarad input capacitance is used here. It belongs to the family of electronic devices known as AUP/ULP/V. In this case, the electronic component is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 5. In this device, the clock edge trigger type is Positive Edge. An electronic part designed with 1bits is used in this application. The maximal supply voltage (Vsup) reaches 3.6V. The supply voltage (Vsup) should be kept above 0.8V for normal operation. Quiescent current is consumed by the D latch in the amount of 500nA.

74AUP1G79GX,125 Features

Tape & Reel (TR) package
74AUP series
5 pins
1 Bits

74AUP1G79GX,125 Applications

There are a lot of Nexperia USA Inc. 74AUP1G79GX,125 Flip Flops applications.

• Bounce elimination switch
• Computing
• Event Detectors
• Parallel data storage
• Count Modes
• Safety Clamp
• Data transfer
• ESCC
• Circuit Design
• 2 – Bit synchronous counter