74AUP2G79GS,115 Overview

The flip flop is packaged in 8-XFDFN. It is contained within the Tape & Reel (TR)package. T flip flop uses Non-Invertedas its output configuration. The trigger configured with it uses Positive Edge. This electronic part is mounted in the way of Surface Mount. Powered by a 0.8V~3.6Vvolt supply, it operates as follows. In this case, the operating temperature is -40°C~125°C TA. The type of this D latch is D-Type. JK flip flop is a part of the 74AUPseries of FPGAs. In order for it to function properly, its output frequency should not exceed 309MHz. A total of 2elements are present in it. T flip flop consumes 500nA quiescent energy. The number of terminations is 8. D latch belongs to the 74AUP2G79 family. Power is supplied from a voltage of 1.1V volts. The input capacitance of this JK flip flopis 0.6pF farads. AUP/ULP/Vis the family of this D flip flop. In this case, the electronic component is mounted in the way of Surface Mount. A total of 8pins are provided on this board. Its clock edge trigger type is Positive Edge. 3.6Vis the maximum supply voltage (Vsup).

74AUP2G79GS,115 Features

Tape & Reel (TR) package
74AUP series
8 pins

74AUP2G79GS,115 Applications

There are a lot of Nexperia USA Inc. 74AUP2G79GS,115 Flip Flops applications.

• Clock pulse
• Divide a clock signal by 2 or 4
• 2 – Bit synchronous counter
• EMI reduction circuitry
• Latch
• Balanced Propagation Delays
• Buffered Clock
• Supports Live Insertion
• Digital electronics systems
• Control circuits