74AUP2G79GT,115 Overview

The flip flop is packaged in a case of 8-XFDFN. It is contained within the Tape & Reel (TR)package. As configured, the output uses Non-Inverted. It is configured with a trigger that uses Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 0.8V~3.6V volts. A temperature of -40°C~125°C TAis used in the operation. D-Typeis the type of this D latch. This type of FPGA is a part of the 74AUP series. A frequency of 309MHzshould be the maximum output frequency. In total, it contains 2 elements. Despite external influences, it consumes 500nAof quiescent current. There are 8 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. Members of the 74AUP2G79family make up this object. The power source is powered by 1.2V. The input capacitance of this T flip flop is 0.6pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. It is a member of the AUP/ULP/Vfamily of D flip flop. There is a 3.6Vmaximum supply voltage (Vsup). A normal operating voltage (Vsup) should remain above 0.8V.

74AUP2G79GT,115 Features

Tape & Reel (TR) package
74AUP series

74AUP2G79GT,115 Applications

There are a lot of Nexperia USA Inc. 74AUP2G79GT,115 Flip Flops applications.

• Load Control
• Computers
• Convert a momentary switch to a toggle switch
• Frequency Dividers
• Clock pulse
• Buffered Clock
• Shift registers
• Communications
• ESD performance
• Dynamic threshold performance