1.65V~3.6V 230MHz 8 Bit D-Type Flip Flop DUAL 74LVC273 20 Pins 10μA 74LVC Series 20-TSSOP (0.173, 4.40mm Width)
SOT-23
74LVC273PW,118 Datasheet
non-compliant
In-Stock: 0 items
Specifications
Name
Value
Type
Parameter
Factory Lead Time
4 Weeks
Contact Plating
Gold
Mount
Surface Mount
Mounting Type
Surface Mount
Package / Case
20-TSSOP (0.173, 4.40mm Width)
Number of Pins
20
Operating Temperature
-40°C~125°C TA
Packaging
Tape & Reel (TR)
Published
2006
Series
74LVC
JESD-609 Code
e4
Part Status
Active
Moisture Sensitivity Level (MSL)
1 (Unlimited)
Number of Terminations
20
Type
D-Type
Technology
CMOS
Voltage - Supply
1.65V~3.6V
Terminal Position
DUAL
Terminal Form
GULL WING
Supply Voltage
1.8V
Terminal Pitch
0.65mm
Base Part Number
74LVC273
Function
Master Reset
Output Type
Non-Inverted
Number of Elements
1
Polarity
Non-Inverting
Supply Voltage-Max (Vsup)
3.6V
Number of Bits
8
Clock Frequency
230MHz
Propagation Delay
11.5 ns
Quiescent Current
100nA
Turn On Delay Time
1.5 ns
Family
LVC/LCX/Z
Logic Function
D-Type, Flip-Flop
Current - Quiescent (Iq)
10μA
Current - Output High, Low
24mA 24mA
Max Propagation Delay @ V, Max CL
8.2ns @ 3.3V, 50pF
Trigger Type
Positive Edge
Input Capacitance
5pF
Number of Input Lines
8
Clock Edge Trigger Type
Positive Edge
Length
6.5mm
Width
4.4mm
Radiation Hardening
No
REACH SVHC
No SVHC
RoHS Status
ROHS3 Compliant
Lead Free
Lead Free
Pricing & Ordering
Quantity
Unit Price
Ext. Price
1
$0.61000
$0.61
500
$0.6039
$301.95
1000
$0.5978
$597.8
1500
$0.5917
$887.55
2000
$0.5856
$1171.2
2500
$0.5795
$1448.75
74LVC273PW,118 Product Details
74LVC273PW,118 Overview
The package is in the form of 20-TSSOP (0.173, 4.40mm Width). The package Tape & Reel (TR)contains it. T flip flop is configured with an output of Non-Inverted. This trigger is configured to use Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. Powered by a 1.65V~3.6Vvolt supply, it operates as follows. Temperature is set to -40°C~125°C TA. The type of this D latch is D-Type. In FPGA terms, D flip flop is a type of 74LVCseries FPGA. You should not exceed 230MHzin the output frequency of the device. A total of 1 elements are present. T flip flop consumes 10μA quiescent energy. There have been 20 terminations. The 74LVC273family includes it. The D flip flop is powered by a voltage of 1.8V . JK flip flop input capacitance is 5pF farads. In terms of electronic devices, this device belongs to the LVC/LCX/Zfamily of devices. A part of the electronic system is mounted in the way of Surface Mount. 20pins are included in its design. There is a clock edge trigger type of Positive Edgeon this device. Flip flops designed with 8bits are used in this part. It reaches 3.6Vwhen the maximum supply voltage (Vsup) is applied. There are 8 input Lines, which consist of an electronic circuit connected between the ac mains and the rectifier input stage of the switching power supply. It consumes a total of 100nA quiescent current at any given time.