STB270N4F3 datasheet pdf and Transistors - FETs, MOSFETs - Single product details from STMicroelectronics stock available on our website
SOT-23
STB270N4F3 Datasheet
non-compliant
In-Stock: 0 items
Specifications
Name
Value
Type
Parameter
Factory Lead Time
12 Weeks
Lifecycle Status
ACTIVE (Last Updated: 8 months ago)
Mount
Surface Mount
Mounting Type
Surface Mount
Package / Case
TO-263-3, D2Pak (2 Leads + Tab), TO-263AB
Number of Pins
3
Transistor Element Material
SILICON
Operating Temperature
-55°C~175°C TJ
Packaging
Tape & Reel (TR)
Series
Automotive, AEC-Q101, STripFET™ III
JESD-609 Code
e3
Part Status
Active
Moisture Sensitivity Level (MSL)
1 (Unlimited)
Number of Terminations
2
ECCN Code
EAR99
Resistance
2MOhm
Terminal Finish
Matte Tin (Sn)
Subcategory
FET General Purpose Power
Technology
MOSFET (Metal Oxide)
Terminal Form
GULL WING
Peak Reflow Temperature (Cel)
245
[email protected] Reflow Temperature-Max (s)
30
Base Part Number
STB270N
Pin Count
4
JESD-30 Code
R-PSSO-G2
Number of Elements
1
Power Dissipation-Max
330W Tc
Element Configuration
Single
Operating Mode
ENHANCEMENT MODE
Power Dissipation
330W
Case Connection
DRAIN
Turn On Delay Time
22 ns
FET Type
N-Channel
Transistor Application
SWITCHING
Rds On (Max) @ Id, Vgs
2.5m Ω @ 80A, 10V
Vgs(th) (Max) @ Id
4V @ 250μA
Input Capacitance (Ciss) (Max) @ Vds
7400pF @ 25V
Current - Continuous Drain (Id) @ 25°C
160A Tc
Gate Charge (Qg) (Max) @ Vgs
150nC @ 10V
Rise Time
180ns
Drive Voltage (Max Rds On,Min Rds On)
10V
Vgs (Max)
±20V
Fall Time (Typ)
45 ns
Turn-Off Delay Time
110 ns
Continuous Drain Current (ID)
160A
Gate to Source Voltage (Vgs)
20V
Drain to Source Breakdown Voltage
40V
Pulsed Drain Current-Max (IDM)
640A
Radiation Hardening
No
RoHS Status
ROHS3 Compliant
Lead Free
Lead Free
Pricing & Ordering
Quantity
Unit Price
Ext. Price
STB270N4F3 Product Details
STB270N4F3 N-Channel MOSFET Description
This N-Channel enhancement mode MOSFETSTB270N4F3 is the most recent improvement of STMicroelectronics' distinctive "Single Feature SizeTM" strip-based process, with fewer key alignment stages and thus exceptional manufacturing reproducibility. The resulting transistor has a very high packing density for low on-resistance, tough avalanche properties, and a low gate charge.