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74ALVCH16374ZRDR

74ALVCH16374ZRDR

74ALVCH16374ZRDR

Texas Instruments

1.65V~3.6V 150MHz D-Type Flip Flop 74ALVCH16374 40μA 74ALVCH Series 54-TFBGA

SOT-23

74ALVCH16374ZRDR Datasheet PDF

non-compliant

Technical Specifications

Parameter NameValue
TypeParameter
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 54-TFBGA
Operating Temperature-40°C~85°C TA
PackagingTape & Reel (TR)
Series 74ALVCH
Part StatusObsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Type D-Type
Voltage - Supply 1.65V~3.6V
Base Part Number 74ALVCH16374
Function Standard
Output Type Tri-State, Non-Inverted
Number of Elements 2
Clock Frequency 150MHz
Turn On Delay Time1 ns
Current - Quiescent (Iq) 40μA
Current - Output High, Low 24mA 24mA
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 4.2ns @ 3.3V, 50pF
Trigger Type Positive Edge
Input Capacitance3pF
Clock Edge Trigger Type Positive Edge
RoHS StatusROHS3 Compliant
In-Stock:1333 items

74ALVCH16374ZRDR Product Details

74ALVCH16374ZRDR Overview


54-TFBGAis the packaging method. D flip flop is included in the Tape & Reel (TR)package. The output it is configured with uses Tri-State, Non-Inverted. This trigger uses the value Positive Edge. Surface Mountis in the way of this electric part. Powered by a 1.65V~3.6Vvolt supply, it operates as follows. In this case, the operating temperature is -40°C~85°C TA. It is an electronic flip flop with the type D-Type. The FPGA belongs to the 74ALVCH series. You should not exceed 150MHzin its output frequency. A total of 2elements are present in it. T flip flop consumes 40μA quiescent energy. You can search similar parts based on 74ALVCH16374. The input capacitance of this JK flip flopis 3pF farads. A part of the electronic system is mounted in the way of Surface Mount. It has a clock edge trigger type of Positive Edge.

74ALVCH16374ZRDR Features


Tape & Reel (TR) package
74ALVCH series

74ALVCH16374ZRDR Applications


There are a lot of Texas Instruments 74ALVCH16374ZRDR Flip Flops applications.

  • Computing
  • ESD protection
  • Bus hold
  • Dynamic threshold performance
  • Individual Asynchronous Resets
  • Asynchronous counter
  • Set-reset capability
  • Buffered Clock
  • Matched Rise and Fall
  • Single Up Count-Control Line

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