74AUP2G80GD,125 Overview

The item is packaged in 8-XFDFNcases. As part of the package Tape & Reel (TR), it is embedded. There is a Invertedoutput configured with it. There is a trigger configured with Positive Edge. Surface Mountmounts this electrical part. The JK flip flop operates with an input voltage of 0.8V~3.6V volts. It is operating at -40°C~125°C TA. D-Typedescribes this flip flop. FPGAs belonging to the 74AUPseries contain this type of chip. Its output frequency should not exceed 309MHz Hz. There are 2 elements in it. There have been 8 terminations. This D latch belongs to the family of 74AUP2G80. Power is provided by a 1.2V supply. This T flip flop has a capacitance of 0.6pF farads at the input. The electronic device belongs to the AUP/ULP/Vfamily. Electronic part Surface Mountis mounted in the way. It is designed with 8 pins. A Positive Edgeclock edge trigger is used in this device. The RS flip flops belongs to FF/Latches base part number. The design is based on 1bits. 3.6Vis the maximum supply voltage (Vsup). As a result of its reliable performance, this T flip flop is suitable for TAPE AND REEL. There are 1 output Lines, which generate the binary equivalent of the input line whose value is equal to “1” and are available to encode either a decimal or hexadecimal input pattern to typically a binary or “B. C. D” (binary coded decimal) output code. It consumes 500nA of quiescent current without being affected by external factors.

74AUP2G80GD,125 Features

Tape & Reel (TR) package
74AUP series
8 pins
1 Bits

74AUP2G80GD,125 Applications

There are a lot of Nexperia USA Inc. 74AUP2G80GD,125 Flip Flops applications.

• Dynamic threshold performance
• Computers
• Balanced Propagation Delays
• Communications
• Automotive
• Clock pulse
• Parallel data storage
• 2 – Bit synchronous counter
• Data storage
• Latch